The present invention relates to a semiconductor integrated circuit device and a method for fabricating the same. More particularly, it relates to technology for forming a linear pattern composed of the gate electrode and wires of a MOS transistor, or metal wires, and the like in a system LSI in which a group of elements having an extremely fine repetitive pattern, such as DRAMs (Dynamic Random Access Memories), can be merged.
As an example of a semiconductor integrated circuit device in which DRAMs are merged, a system LSI on which DRAMs having a capacity over 20 megabits are mounted has been mass-produced in recent years.
In the fabrication steps for a semiconductor integrated circuit device represented by the system LSI in which the mounting rate of memory circuits such as DRAMs, SRAMs (Static Random Access Memories), or ROMs (Read Only Memories) on a single semiconductor chip (rate of an area occupied by the memory circuits to an area of the entire chip; hereinafter also referred to as an area-occupying rate) differs according to usage or specifications, the formation of a mask pattern having not only unit circuits which are simply and repeatedly arranged therein but also a variety of layouts has been required.
There has conventionally been known a phenomenon in which the configuration or size of a pattern obtained by etching a target film by using a mask pattern (hereinafter referred to as a formed pattern) differs depending on a mask pattern layout, i.e., the placement of an element pattern.
As an example of the phenomenon, a pattern proximity effect occurring during the formation of a resist pattern in a photolithographic step can be listed. This is the phenomenon in which even a pattern having the same design configuration and the same design size has different configurations and sizes after it is formed depending on the degree of proximity between the pattern and a pattern adjacent thereto or on the configuration of the adjacent pattern.
As another example, there can be listed a loading effect or a microloading effect occurring in a dry etching step. The loading effect is a phenomenon in which an etching rate varies depending on the size of a total etched area of a semiconductor chip, which may slightly affect variations in pattern size. The microloading effect is a phenomenon in which, when a pattern laid out in a single semiconductor chip shows an arrangement which is locally sparse and dense, an etching rate differs locally due to the locally dense and sparse arrangement. That is, the etching rate for even the single chip differs from the portion thereof on which the pattern is sparsely placed to the portion thereof on which the pattern is densely placed, which also indirectly affects variations in pattern size.
To solve the foregoing problem of variations in pattern size depending on the mask pattern layout, there have conventionally been adopted such design rules as to correct variations in pattern size only at a portion of a mask where the pattern size is considered to vary remarkably depending on the mask pattern layout due to the proximity effect or the loading effect.
On the other hand, the fabrication of a system LSI in which DRAMs can be merged has used the same processing method or the same processing condition irrespective of the presence or absence of a mounted DRAM or of a DRAM area-occupying rate (the rate of an area occupied by the DRAMs to the area of an entire chip).
With the increasing miniaturization of the LSI, specifically as the size of an integrated circuit pattern is reduced to 0.25 xcexcm or less, particularly to 0.15 xcexcm or less, higher-precision size control has been required so that size variations resulting from difference in mask pattern layout are no more negligible.
FIG. 8 shows the frequency distribution of a CD (critical dimension) loss which is the difference between the size of a resist pattern prior to etching and the size of a completed gate electrode when the gate electrode is formed by dry etching by using the resist pattern as a mask in the fabrication of each of semiconductor integrated circuit devices on which 24 Mb DRAMs are mounted (hereinafter referred to as a DRAM mounted type) and a semiconductor integrated circuit device on which DRAMs are not mounted (hereinafter referred to as a DRAM unmounted type). The result shown in FIG. 8 was obtained by using the same gate-electrode forming process in the fabrication of each of the DRAM mounted type and the DRAM unmounted type. Each of the CD losses was calculated by subtracting the size of the completed gate electrode from the size of the resist pattern prior to etching.
As shown in FIG. 8, mask-pattern-layout dependency is observed in pattern size though the same gate-electrode forming process was used to fabricate each of the types.
This indicates that, in accordance with the conventional method for fabricating a semiconductor integrated circuit device, the gate electrode size varies with difference in mask pattern layout associated with different types of semiconductor integrated circuit devices even if the same gate-electrode forming process is used. In other words, type dependency occurs in gate electrode size. As a result, the characteristics of a MOS transistor deviate from design specifications in a specified type of semiconductor integrated circuit device fabricated by using a specified mask, which causes the problem of a narrower operating margin. The problem cannot be ignored especially when the design rules are 0.18 xcexcm or less.
In view of the foregoing, it is therefore an object of the present invention to prevent a size variation resulting from difference in mask pattern layout during the formation of a linear pattern composed of the gate electrode and wires of a MOS transistor, or metal wires, and the like.
To attain the object the present inventors have examined the cause of size variations resulting from difference in mask pattern layout.
As a result the examination, the present inventors have found that, in a semiconductor integrated circuit device on which a logic circuit composed of a CMOS (Complementary Metal-Oxide Semiconductor) is mounted and a memory circuit such as a DRAM composed of the gate electrode and wires that are densely arranged is mounted, pattern size varies with the area-occupying rate of the memory circuit.
The present inventors have also found that the phenomenon in which size variations result from difference in mask pattern layout is different in nature from the foregoing loading effect which results from the size of the etched area, i.e., the area of the pattern. As is obvious from FIG. 8, the phenomenon is a phenomenon of novel nature in which the pattern size varies over the entire chip, which is also different from the microloading effect resulting from the in-chip local denseness and sparseness of the pattern.
As described above, the type dependency of the size of the formed gate electrode or the like results from the CD loss. On the other hand, a dry etching step currently performed uses an etching gas having a sidewall protecting effect (hereinafter referred to as a deposition gas) or forms an etching reaction product having the sidewall protecting effect to achieve anisotropic dry etching by preventing side etching. If a gate electrode is formed by performing dry etching with respect to a polysilicon film, a chlorine-containing gas, e.g., is used frequently as the etching gas and HBr gas is used frequently as the deposition gas. As a result, a sidewall protecting film composed of SiBr4, which is a reaction product between HBr and polysilicon and has low volatility, is formed on a sidewall of the polysilicon film. In the case of forming aluminium wires by performing dry etching with respect to an aluminium film, a CHF3 gas has been used frequently as the deposition gas in recent years. The CHF3 gas containing fluorine is a depositive gas added to form the sidewall protecting film but does not contribute to the etching of the aluminium film.
The present inventors have found that, if the configuration of the target film after etching is to be controlled with the sidewall protecting effect in the case of using the same gate-electrode forming process irrespective of the mask pattern layout, the sidewall protecting effect per unit area is reduced as the area of the sidewall of the target film to be protected increases, which increases the CD loss.
FIG. 9 shows the relationship between the perimeter of a gate electrode per unit area (the length of the peripheral portion of the gate electrode) and the DRAM area-occupying rate in each of various types of semiconductor integrated circuit devices having different DRAM area-occupying rates including the DRAM unmounted type. In the graph of FIG. 9, xe2x80x9cPerimeter of Gate Electrode Per Unit Areaxe2x80x9d represented by the vertical axis indicates the value obtained by dividing the total perimeter of the gate electrodes in a specified circuit region by the area of the specified circuit region. The specified circuit region may be the entire chip.
As shown in FIG. 9, the perimeter of the gate electrode per unit area increases as the DRAM area-occupying rate increases.
FIG. 10 shows the relationship between the perimeter of the gate electrode per unit area and the CD loss in each of the various types.
As shown in FIG. 10, the size of the gate electrode decreases as the perimeter of the gate electrode per unit area increases (the CD loss becomes positive). Conversely, the size of the gate electrode increases as the perimeter of the gate electrode per unit area decreases (the CD loss becomes negative). This is because the area of the sidewall to be protected increases as the perimeter of the gate electrode per unit area increases so that the sidewall protecting effect per unit area is reduced accordingly.
The present inventors have focused attention on the fact that the CD loss changes monotonously from a negative value to a positive value as the perimeter of the gate electrode per unit area increases (see FIG. 10) and found that size variations in gate electrode pattern resulting from difference in mask pattern layout can be prevented by setting the perimeter of the gate electrode per unit area in a specified range irrespective of the type or adjusting a process condition in accordance with type-to-type difference in the perimeter per unit area of the gate electrode.
Specifically, a first semiconductor integrated circuit device according to the present invention assumes a semiconductor integrated circuit device comprising: a circuit pattern having a linear pattern, a perimeter of the linear pattern per unit area being set in a specified range.
In the first semiconductor integrated circuit device, the perimeter of the linear pattern per unit area is set in the specified range. Accordingly, even if a mask pattern layout differs greatly from one type of semiconductor integrated circuit device to another, size variations in linear pattern resulting from difference in mask pattern layout can be prevented. In a system LSI in which the mounting rate of DRAMs or the like is different depending on use or specifications also, it is possible to form gate electrode patterns, metal wires, or the like of uniform sizes irrespective of the mask pattern layout, so that a semiconductor integrated circuit device free of variations in operating margin is provided.
A second semiconductor integrated circuit device according to the present invention assumes a semiconductor integrated circuit device comprising: a circuit pattern having a linear pattern, a dummy pattern being inserted in a region in which the circuit pattern is placed such that a sum perimeter of the linear pattern and the dummy pattern per unit area is set in a specified range.
In the second semiconductor integrated circuit device, the sum perimeter of the linear pattern and the dummy pattern per unit area is set in the specified range. Accordingly, even if a mask pattern layout differs greatly from one type of semiconductor integrated circuit device to another, size variations in linear pattern resulting from difference in mask pattern layout can be prevented. In a system LSI in which the mounting rate of DRAMs or the like is different depending on use or specifications also, it is possible to form gate electrode patterns, metal wires, or the like of uniform sizes irrespective of the mask pattern layout, so that a semiconductor integrated circuit device free of variations in operating margin is provided.
In the second semiconductor integrated circuit device, the dummy pattern preferably has a strip-like configuration.
This allows easy formation of the dummy pattern.
A third semiconductor integrated circuit device according to the present invention assumes a semiconductor integrated circuit device comprising: a first circuit pattern having a first linear pattern and placed in a region in which a group of elements having a repetitive pattern are formed; and a second circuit pattern having a second linear pattern and placed in a region in which components other than the group of elements are formed, a dummy pattern being inserted in the region in which the second circuit pattern is placed such that a sum perimeter of the first linear pattern, the second linear pattern, and the dummy pattern per unit area is equal to or less than a perimeter of the first linear pattern per unit area.
In the third semiconductor integrated circuit device, the dummy pattern is inserted in the region in which the second circuit pattern corresponding to the components other than the group of elements is placed, whereby the sum perimeter per unit area of the first linear pattern of the first circuit pattern corresponding to the group of elements, the second linear pattern of the second circuit pattern, and the dummy pattern is set to the perimeter of the first linear pattern per unit area, i.e., the largest perimeter per unit area or less. Specifically, the sum perimeter per unit area is preferably set to 70% to 100% of the perimeter per unit area of the first linear pattern. Since the sum perimeter per unit area is set in the specified range, even if a mask pattern layout differs greatly from one type of semiconductor integrated circuit device to another, size variations in linear pattern resulting from difference in mask pattern layout can be prevented. In a system LSI in which the mounting rate of DRAMs or the like is different depending on use or specifications also, it is possible to form gate electrode patterns, metal wires, or the like of uniform sizes irrespective of the mask pattern layout, so that a semiconductor integrated circuit device free of variations in operating margin is provided.
In the third the semiconductor integrated circuit, the group of elements are preferably memories.
In the third the semiconductor integrated circuit, a perimeter of the dummy pattern per unit area is preferably 70% or more of the perimeter of the first linear pattern per unit area.
The insertion of the dummy pattern ensures the setting of the sum perimeter per unit area in the specified range, specifically 70% to 100% of the perimeter of the first linear pattern per unit area.
A first method for fabricating a semiconductor integrated circuit device assumes a method for fabricating a plurality of semiconductor integrated circuit devices each comprising a circuit pattern having a linear pattern, at least one of fabrication steps for the semiconductor integrated circuit devices being common, the fabrication steps including the step of: inserting a dummy pattern in a region in which the circuit pattern is placed such that a sum perimeter of the linear pattern and the dummy pattern per unit area is set in a specified range.
In accordance with the first method for fabricating a semiconductor integrated circuit device, the dummy pattern is inserted such that the sum perimeter of the linear pattern and the dummy pattern per unit area is set in the specified range. Specifically, it is desirable to assume, as the specified range, 70% to 100% of the perimeter of the linear pattern per unit area in a memory circuit. To satisfy the standard, the perimeter of the inserted dummy pattern per unit area should be 70% or more of the perimeter of the linear pattern per unit area in the memory circuit. The present inventors have found that the CD loss in the formed pattern or the size of the formed pattern changes depending on the perimeter of the formed pattern per unit area. Accordingly, even if a mask pattern layout differs greatly from one type of semiconductor integrated circuit device to another, the sum perimeter of the linear pattern and the dummy pattern per unit area can be set in the specified range by forming an additional dummy pattern having a perimeter per unit area of 70% or more of that of the linear pattern of the memory circuit in a vacant region. For example, the perimeter of the gate electrode per unit area over the entire chip is largely dependent on a specified circuit such as a memory circuit since the specified circuit has a large perimeter of the gate electrode per unit area. Even if the in-chip area-occupying rate of such a specified circuit varies from one type to another, variations in the perimeter of the gate electrode per unit area over the entire chip can be suppressed by using the dummy pattern, as described above. As a result, size variations resulting from difference in mask pattern layout can be prevented. In short, the linear pattern can constantly be formed by etching with high precision. In a system LSI in which the mounting rate of DRAMs, SRAMs, ROMS, or the like is different depending on use or specifications also, it is possible to form the gate electrode and wires for MOS transistors, metal wires, or the like of uniform sizes irrespective of the mask pattern layout, so that a semiconductor integrated circuit device free of variations in operating margin is provided.
A second method for fabricating a semiconductor integrated circuit device assumes a method for fabricating a semiconductor integrated circuit device, the method comprising the steps of: exposing each of a plurality of first regions of a semiconductor substrate to transfer a circuit pattern having a linear pattern onto the first region; exposing each of a plurality of second regions of the semiconductor substrate other than the first regions to transfer a dummy pattern onto the second region; and adjusting a ratio between the number of exposing shots for transferring the circuit pattern and the number of exposing shots for transferring the dummy pattern such that a sum perimeter of all the linear patterns transferred and all the dummy patterns transferred per unit area is set in a specified range.
In accordance with the second method for fabricating a semiconductor integrated circuit device, the ratio between the number of exposing shots for transferring the circuit pattern and the number of exposing shots for transferring the dummy pattern is adjusted such that the sum perimeter of all the linear patterns transferred and all the dummy patterns transferred per unit area is set in the specified range. Accordingly, even if a mask pattern layout differs greatly from one type of semiconductor integrated circuit device to another, size variations in linear pattern resulting from difference in mask pattern layout can be prevented. In a system LSI in which the mounting rate of DRAMs or the like is different depending on use or specifications also, it is possible to form gate electrode patterns, metal wires, or the like of uniform sizes irrespective of the mask pattern layout, so that a semiconductor integrated circuit device free of variations in operating margin is provided.
A third method for fabricating a semiconductor integrated circuit devices assumes a method for fabricating a plurality of semiconductor integrated circuit devices each comprising a circuit pattern having a linear pattern, at least one of fabrication steps for the semiconductor integrated circuit devices being common, the fabrication steps including the step of: performing dry etching with respect to a target film while adjusting a dry etching condition in accordance with a perimeter of the linear pattern per unit area.
In accordance with the third method for fabricating a semiconductor integrated circuit device, dry etching is performed with respect to the target film while adjusting the dry etching condition in accordance with the perimeter of the linear pattern per unit area. Accordingly, even if a mask pattern layout differs greatly from one type of semiconductor integrated circuit device to another, the size of the linear pattern can be held constantly at a specified value. In a system LSI in which the mounting rate of DRAMs or the like is different depending on use or specifications also, it is possible to form gate electrode patterns, metal wires, or the like of uniform sizes irrespective of the mask pattern layout, so that a semiconductor integrated circuit device free of variations in operating margin is provided.
In the third method for fabricating a semiconductor integrated circuit device, the step of adjusting the dry etching condition preferably includes the step of: determining one dry etching condition when the perimeter of the linear pattern per unit area is within one range.
The arrangement allows easy adjustment of the dry etching condition.
A fourth method for fabricating a semiconductor integrated circuit device assumes a method for fabricating a plurality of semiconductor integrated circuit devices each comprising a circuit pattern having a linear pattern, at least one of fabrication steps for the semiconductor integrated circuit devices being common, the fabrication steps including the step of: forming a resist pattern corresponding to the linear pattern while adjusting a size of the resist pattern in accordance with a perimeter of the linear pattern per unit area.
In accordance with the fourth method for fabricating a semiconductor integrated circuit device, the resist pattern corresponding to the linear pattern is formed while the size of the resist pattern is adjusted in accordance with the perimeter of the linear pattern per unit area. Accordingly, even if a mask pattern layout differs greatly from one type of semiconductor integrated circuit device to another, the size of the linear pattern can be held constantly at a specified value. In a system LSI in which the mounting rate of DRAMs or the like is different depending on use or specifications also, it is possible to form gate electrode patterns, metal wires, or the like of uniform sizes irrespective of the mask pattern layout, so that a semiconductor integrated circuit device free of variations in operating margin is provided.
A fifth method for fabricating a semiconductor integrated circuit devices assumes a method for fabricating a plurality of semiconductor integrated circuit devices each comprising a circuit pattern having a linear pattern, at least one of fabrication steps for the semiconductor integrated circuit devices being common, the fabrication steps including: a first step of forming a resist pattern corresponding to the linear pattern on a target film; and a second step of performing dry etching with respect to the target film by using the resist pattern as a mask, the second step including the step of: using an etching gas having an effect of protecting a sidewall formed in the target film through the etching or forming an etching reaction product having the sidewall protecting effect, a processing method or a processing condition in at least one of the first and second steps being adjusted in accordance with a ratio between an area occupied by a group of elements contained in the circuit pattern and having a repetitive pattern and an area of a region in which the circuit pattern is placed.
In the first step of forming the resist pattern corresponding to the linear pattern or in the second step of performing dry etching with respect to the target film by using the resist pattern as a mask, the fifth method for fabricating a semiconductor integrated circuit device changes the processing method or the processing condition in accordance with the rate of the area occupied by the group of elements having the repetitive pattern to the area of the region in which the circuit pattern is placed (hereinafter referred to as a group-of-elements area-occupying rate). Accordingly, even if the area of the sidewall formed in the target film through etching differs according to difference in group-of-elements area-occupying rates, i.e., difference in mask pattern layout, it is possible to adjust the size of the resist pattern in the first step so as to eliminate difference in sidewall protecting effects per unit area in the second step or adjust the etching condition in the second step to achieve a desired sidewall protecting effect per unit area. This prevents size variations resulting from difference in mask pattern layout during the formation of the circuit pattern by using a lithographic or dry etching technique and thereby allows high-precision formation of a gate electrode or wires.
In the fifth method for fabricating a semiconductor integrated circuit device, the group of elements are preferably memories such as DRAMs.
In the fifth method for fabricating a semiconductor integrated circuit device, the first step preferably includes the step of: increasing a size of the resist pattern as the group-of-elements area-occupying rate increases.
In the arrangement, the area of the sidewall formed in the target film through etching increases as the group-of-elements area-occupying rate increases. Accordingly, even if the sidewall protecting effect per unit area decreases in the second step, the decrement in sidewall protecting effect can be compensated for so that size variations in components are surely suppressed.
In the fifth method for fabricating a semiconductor integrated circuit device, the second step preferably includes the step of: determining an etching condition such that the sidewall protecting effect increases as the group-of-elements area occupying rate increases.
In the arrangement, even if the area of the sidewall formed in the target film through etching increases as the group-of-elements area-occupying rate increases, a desired sidewall protecting effect per unit area is achievable in the second step that so that size variations in components are surely suppressed.